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data sheet 10.97 mi c r o c omp u ter componen t s c517a 8-bit cmos microcontroller
c517a data sheet revision history: current version: 10.97 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision) edition 10.97 published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1997. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered.
semiconductor group 3 1997-10-01 8-bit cmos microcontroller advance information c517a ? full upward compatibility with sab 80c517a/83c517a-5 ? up to 24 mhz external operating frequency C 500 ns instruction cycle at 24 mhz operation ? superset of the 8051 architecture with 8 datapointers ? on-chip emulation support logic (enhanced hooks technology tm ) ? 32k byte on-chip rom (with optional rom protection) C alternatively up to 64k byte external program memory ? up to 64k byte external data memory ? 256 byte on-chip ram ? additional 2k byte on-chip ram (xram) ? seven 8-bit parallel i/o ports ? two input ports for analog/digital input (further features are on next page) figure 1 c517a functional units mca03317 port 0 port 1 port 2 xram ram t0 t1 mdu rom i/o (8 datapointer) i/o analog/ digital input port 3 32k x 8 cpu port 8 input digital analog/ 256 x 8 2k x 8 port 7 port 6 port 5 port 4 watchdog timer oscillator watchdog 10-bit a/d converter 8 bit usart uart 8 bit timer compare t2 ccu power saving modes on-chip emulation support module i/o i/o i/o i/o i/o
c517a semiconductor group 4 1997-10-01 features (contd): ? two full duplex serial interfaces (usart) C 4 operating modes, fixed or variable baud rates C programmable baud rate generators ? four 16-bit timer/counters C timer 0 / 1 (c501 compatible) C timer 2 for 16-bit reload, compare, or capture functions C compare timer for compare/capture functions ? powerful 16-bit compare/capture unit (ccu) with up to 21 high-speed or pwm output channels and 5 capture inputs ? 10-bit a/d converter C 12 multiplexed analog inputs C built-in self calibration ? extended watchdog facilities C 15-bit programmable watchdog timer C oscillator watchdog ? power saving modes C slow down mode C idle mode (can be combined with slow down mode) C software power-down mode C hardware power-down mode ? 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels ? p-mqfp-100 packages ? temperature ranges: sab-c517a t a = 0 to 70 c saf-c517a t a = -40 to 85 c sah-c517a t a = -40 to 110 c table 1 ordering information type ordering code package description (8-bit cmos microcontroller) sab-c517a-4rm q67120-dxxxx p-mqfp-100-2 with mask programmable rom (18 mhz) SAF-C517A-4RM q67120-dxxxx p-mqfp-100-2 with mask programmable rom (18 mhz) ext. temp. C 40 c to 85 c sab-c517a-4r24m q67120-dxxxx p-mqfp-100-2 with mask programmable rom (24 mhz) saf-c517a-4r24m q67120-dxxxx p-mqfp-100-2 with mask programmable rom (24 mhz) ext. temp. C 40 c to 85 c sab-c517a-lm q67127-c1071 p-mqfp-100-2 for external memory (18 mhz) saf-c517a-lm q67127-c1063 p-mqfp-100-2 for external memory (18 mhz) ext. temp. C 40 c to 85 c sab-c517a-l24m q67127-c1072 p-mqfp-100-2 for external memory (24 mhz)
semiconductor group 5 1997-10-01 c517a note: versions for extended temperature ranges C 40 c to 110 c (sah-c517a) are available on request. the ordering number of rom types (dxxxx extensions) is defined after program release (verification) of the customer. figure 2 logic symbol additional literature for further information about the c517a the following literature is available: title ordering number c517a 8-bit cmos microcontroller users manual b158-h7053-x-x-7600 c500 microcontroller family architecture and instruction set users manual b158-h6987-x-x-7600 c500 microcontroller family - pocket guide b158-h6986-x-x-7600 port 0 8-bit digital i/o port 1 port 2 port 3 port 4 port 5 port 6 mcl03318 c517a 8-bit analog/ port 7 port 8 4-bit analog/ v aref agnd v owe pe/swd ro reset ea ale psen xtal2 xtal1 cc vv ss 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o digital input digital input hwpd
c517a semiconductor group 6 1997-10-01 figure 3 pin configuration p-mqfp-100 package (top view) c517a hwpd mcp03319 p2.6/a14 p0.3/ad3 p1.5/t2ex p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p2.0/a8 xtal1 xtal2 cc1/int4/p1.1 cc2/int5/p1.2 n.c. n.c. n.c. n.c. cc4/int2/p1.4 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ccm7/p5.7 ccm6/p5.6 ccm5/p5.5 ccm1/p5.1 ccm0/p5.0 owe adst/p6.0 rxd1/p6.1 txd1/p6.2 p6.3 p6.4 p4.0/cm0 p4.1/cm1 p4.2/cm2 pe/swd p4.3/cm3 p4.4/cm4 p4.5/cm5 p4.6/cm6 n.c. n.c. n.c. n.c. p1.6/clkout p1.7/t2 p3.7/rd p3.6/wr p3.5/t1 p3.4/t0 p3.3/int1 p3.2/int0 p3.1/txd0 p3.0/rxd0 n.c. n.c. p7.0/ain0 p7.1/ain1 p7.2/ain2 p7.3/ain3 p7.4/ain4 p7.5/ain5 p7.6/ain6 100 31 80 1 ro p8.3/ain11 p8.2/ain10 p8.1/ain9 p8.0/ain8 p6.7 p6.6 p6.5 p2.7/a15 psen ale ea n.c. p0.0/ad0 p0.1/ad1 n.c. v ss cc v v agnd aref v ss v v cc ccm2/p5.2 ccm3/p5.3 ccm4/p5.4 p0.2/ad2 n.c. cc0/int3/p1.0 cc3/int6/p1.3 p7.7/ain7 reset p4.7/cm7 n.c. n.c. n.c. 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 99 32 98 33 97 34 96 35 95 36 94 37 93 38 92 39 91 40 90 41 89 42 88 43 87 44 86 45 85 46 84 47 83 48 82 49 81 50
semiconductor group 7 1997-10-01 c517a table 2 pin de?nitions and functions symbol pin number i/o*) function p-mqfp-100 p1.0 - p1.7 9 - 6, 1, 100 - 98 9 8 7 6 1 100 99 98 i/o port 1 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 1 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. the port is used for the low-order address byte during program verification. port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). the secondary functions are assigned to the port 1 pins as follows: p1.0 int3 cc0 interrupt 3 input / compare 0 output / capture 0 input p1.1 int4 cc1 interrupt 4 input / compare 1 output / capture 1 input p1.2 int5 cc2 interrupt 5 input / compare 2 output / capture 2 input p1.3 int6 cc3 interrupt 6 input / compare 3 output / capture 3 input p1.4 int2 interrupt 2 input p1.5 t2ex timer 2 external reload / trigger input p1.6 clkout system clock output p1.7 t2 counter 2 input v ss 10, 62 C ground (0v) during normal, idle, and power down operation. v cc 11, 63 C supply voltage during normal, idle, and power down mode. *) i = input o = output
c517a semiconductor group 8 1997-10-01 xtal2 12 C xtal2 is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. to drive the device from an external clock source, xtal2 should be driven, while xtal1 is left unconnected. minimum and maximum high and low times as well as rise/ fall times specified in the ac characteristics must be observed. xtal1 13 C xtal1 is the output of the inverting oscillator amplifier. this pin is used for the oscillator operation with crystal or ceramic resonator. p2.0 - p2.7 14 - 21 i/o port 2 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 2 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application it uses strong internal pullup resistors when issuing 1's. during accesses to external data memory that use 8-bit addresses (movx @ri), port 2 issues the contents of the p2 special function register. psen 22 o the program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. it is activated every six oscillator periods except during external data memory accesses. the signal remains high during internal program execution. ale 23 o the address latch enable output is used for latching the address into external memory during normal operation. it is activated every six oscillator periods except during an external data memory access. *) i = input o = output table 2 pin de?nitions and functions (contd) symbol pin number i/o*) function p-mqfp-100
semiconductor group 9 1997-10-01 c517a ea 24 i external access enable when held high, the c517a executes instructions from the internal rom as long as the pc is less than 8000 h . when held low, the c517a fetches all instructions from external program memory. for the c517a-l this pin must be tied low. p0.0 - p0.7 26, 27, 30 - 35 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application it uses strong internal pullup resistors when issuing 1's. port 0 also outputs the code bytes during program verification in the c517a. external pullup resistors are required during program verification. hwpd 36 i hardware power down a low level on this pin for the duration of one machine cycle while the oscillator is running resets the c517a. a low level for a longer period will force the part into hardware power down mode with the pins floating. there is no internal pullup resistor connected to this pin. p5.0 - p5.7 44 - 37 i/o port 5 is a quasi-bidirectional i/o port with internal pull-up resistors. port 5 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 5 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. this port also serves the alternate function concurrent compare and set/reset compare. the secondary functions are assigned to the port 5 pins as follows: ccm0 to ccm7 p5.0 to p5.7: concurrent compare or set/reset lines *) i = input o = output table 2 pin de?nitions and functions (contd) symbol pin number i/o*) function p-mqfp-100
c517a semiconductor group 10 1997-10-01 owe 45 i oscillator watchdog enable a high level on this pin enables the oscillator watchdog. when left unconnected this pin is pulled high by a weak internal pull-up resistor. the logic level at owe should not be changed during normal operation. when held at low level the oscillator watchdog function is turned off. during hardware power down the pullup resistor is switched off. p6.0 - p6.7 46 - 50, 54 - 56 46 47 48 i/o port 6 is a quasi-bidirectional i/o port with internal pull-up resistors. port 6 pins that have 1 s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 6 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. port 6 also contains the external a/d converter control pin and the transmit and receive pins for the serial interface 1. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 6, as follows: p6.0 adst external a/d converter start pin p6.1 rxd1 receiver data input of serial interface 1 p6.2 txd1 transmitter data input of serial interface 1 p8.0 - p8.3 57 - 60 i port 8 is a 4-bit unidirectional input port. port pins can be used for digital input, if voltage levels meet the specified input high/ low voltages, and for the higher 4-bit of the multiplexed analog inputs of the a/d converter, simultaneously. p8.0 - p8.3 ain8 - ain11 analog input 8 - 14 ro 61 o reset output this pin outputs the internally synchronized reset request signal. this signal may be generated by an external hardware reset, a watchdog timer reset or an oscillator watchdog reset. the ro is active low. *) i = input o = output table 2 pin de?nitions and functions (contd) symbol pin number i/o*) function p-mqfp-100
semiconductor group 11 1997-10-01 c517a p4.0 - p4.7 64 - 66, 68 - 72 i/o port 4 is an 8-bit quasi-bidirectional i/o port with internal pull-up resistors. port 4 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. as inputs, port 4 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pull-up resistors. pe/swd 67 i power saving mode enable / start watchdog timer a low level at this pin allows the software to enter the power saving modes (idle mode, slow down mode, and power down mode). in case the low level is also seen during reset, the watchdog timer function is off on default. usage of the software controlled power saving modes is blocked, when this pin is held at high level. a high level during reset performs an automatic start of the watchdog timer immediately after reset. when left unconnected this pin is pulled high by a weak internal pull-up resistor. during hardware power down the pullup resistor is switched off. reset 73 i reset a low level on this pin for the duration of two machine cycles while the oscillator is running resets the c517a. a small internal pullup resistor permits power-on reset using only a capacitor connected to v ss . v aref 78 C reference voltage for the a/d converter v agnd 79 C reference ground for the a/d converter p7.0 - p7.7 87 - 80 port 7 is an 8-bit unidirectional input port. port pins can be used for digital input, if voltage levels meet the specified input high/low voltages, and for the lower 8-bit of the multiplexed analog inputs of the a/d converter, simultaneously. p7.0 - p7.7 ain0 - ain7 analog input 8 - 14 *) i = input o = output table 2 pin de?nitions and functions (contd) symbol pin number i/o*) function p-mqfp-100
c517a semiconductor group 12 1997-10-01 p3.0 - p3.7 90 - 97 90 91 92 93 94 95 96 97 i/o port 3 is an 8-bit quasi-bidirectional i/o port with internal pullup resistors. port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. as inputs, port 3 pins being externally pulled low will source current ( i il , in the dc characteristics) because of the internal pullup resistors. port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. the output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. the secondary functions are assigned to the pins of port 3, as follows: p3.0 rxd0 receiver data input (asynch.) or data input/output (synch.)of serial interface 0 p3.1 txd0 transmitter data output (asynch.) or clock output (synch.) of serial interface 0 p3.2 int0 external interrupt 0 input / timer 0 gate control input p3.3 int1 external interrupt 1 input / timer 1 gate control input p3.4 t0 timer 0 counter input p3.5 t1 timer 1 counter input p3.6 wr wr control output; latches the data byte from port 0 into the external data memory p3.7 rd rd control output; enables the external data memory n.c. 2 - 5, 25, 28, 29, 32, 43, 44, 51 - 53, 74 - 77 88, 89 C not connected these pins of the p-mqfp-100 package need not be connected. *) i = input o = output table 2 pin de?nitions and functions (contd) symbol pin number i/o*) function p-mqfp-100
semiconductor group 13 1997-10-01 c517a figure 4 block diagram of the c517a port 8 port 8 port 7 port 7 port 6 port 6 port 5 port 5 port 4 port 4 port 3 port 3 port 2 port 2 port 1 port 1 8-bit digital i/o port 0 port 0 programmable watchdog timer osc & timing oscillator watchdog serial channel 1 baud rate generator programmable serial channel 0 timer 1 timer 0 timer 2 compare timer capture compare unit s & h analog reset ro ale ea pe/swd aref v v agnd mcb03320 xtal1 xtal2 interrupt unit a/d converter 10 bit emulation support logic rom 32k x 8 2k x 8 xram ram 256 x 8 cpu 8 datapointer programmable baud rate generator mux psen hwpd owe c517a 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o 8-bit analog/ digital input 4-bit analog/ digital input
c517a semiconductor group 14 1997-10-01 cpu the c517a is efficient both as a controller and as an arithmetic processor. it has extensive facilities for binary and bcd arithmetic and excels in its bit-handling capabilities. efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three-byte instructions. with a 12 mhz crystal, 58% of the instructions are executed in 1 m s ( 24 mhz: 500 ns). special function register psw (address d0 h ) reset value : 00 h bit function cy carry flag used by arithmetic instruction. ac auxiliary carry flag used by instructions which execute bcd operations. f0 general purpose flag rs1 rs0 register bank select control bits these bits are used to select one of the four register banks. ov overflow flag used by arithmetic instruction. f1 general purpose flag p parity flag set/cleared by hardware after each instruction to indicate an odd/even number of one bits in the accumulator, i.e. even parity. cy ac f0 rs1 rs0 ov f1 p d0 h psw d7 h d6 h d5 h d4 h d3 h d2 h d1 h d0 h bit no. msb lsb rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
semiconductor group 15 1997-10-01 c517a memory organization the c517a cpu manipulates operands in the following five address spaces: C up to 64 kbyte of program memory (32k on-chip program memory for c517a-4r) C up to 64 kbyte of external data memory C 256 bytes of internal data memory C 2k bytes of internal xram data memory C a 128 byte special function register area figure 5 illustrates the memory address spaces of the c517a. figure 5 c517a memory map ext. ffff 8000 0000 7fff ext. (ea = 0) (ea = 1) int. "code space" int. (xmap0 = 0) (xmap0 = 1) ext. ffff f800 0000 f7ff ext. "data space" "internal data space" internal 7f 00 internal 80 ff function mcb03321 h h h h h h h h h h h h ram ram regs. special indirect address address direct h 80 ff h
c517a semiconductor group 16 1997-10-01 reset and system clock the reset input is an active low input at pin reset. since the reset is synchronized internally, the reset pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. a pullup resistor is internally connected to v cc to allow a power-up reset with an external capacitor only. an automatic reset can be obtained when v cc is applied by connecting the reset pin to v ss via a capacitor. figure 6 shows the possible reset circuitries. figure 6 reset circuitries mcs03323 reset c517a b) a) c) + + & reset reset c517a c517a
semiconductor group 17 1997-10-01 c517a figure 7 shows the recommended oscillator circuitries for crystal and external clock operation. figure 7 recommended oscillator circuitries mcs03245 c c 3.5 - 24 mhz xtal1 xtal2 xtal2 xtal1 n.c. external oscillator signal crystal oscillator mode driving from external source crystal mode: c = 20 pf 10 pf (incl. stray capacitance)
c517a semiconductor group 18 1997-10-01 enhanced hooks emulation concept the enhanced hooks emulation concept of the c500 microcontroller family is a new, innovative way to control the execution of c500 mcus and to gain extensive information on the internal operation of the controllers. emulation of on-chip rom based programs is possible, too. each production chip has built-in logic for the support of the enhanced hooks emulation concept. therefore, no costly bond-out chips are necessary for emulation. this also ensure that emulation and production chips are identical. the enhanced hooks technology tm 1) , which requires embedded logic in the c500 allows the c500 together with an eh-ic to function similar to a bond-out chip. this simplifies the design and reduces costs of an ice-system. ice-systems using an eh-ic and a compatible c500 are able to emulate all operating modes of the different versions of the c500 microcontrollers. this includes emulation of rom, rom with code rollover and romless modes of operation. it is also able to operate in single step mode and to read the sfrs after a break. figure 8 basic c500 mcu enhanced hooks concept configuration port 0, port 2 and some of the control lines of the c500 based mcu are used by enhanced hooks emulation concept to control the operation of the device during emulation and to transfer informations about the program execution and data transfer between the external emulation hardware (ice-system) and the c500 mcu. 1 enhanced hooks technology is a trademark and patent of metalink corporation licensed to siemens. syscon pcon tcon reset ea ale psen port 0 port 2 port 1 port 3 opt. i/o ports c500 mcu 2 rpcon rtcon enhanced hooks interface circuit rsyscon 0 rport rport tea tale tpsen eh-ic ice-system interface to emulation hardware target system interface mcs03254
semiconductor group 19 1997-10-01 c517a special function registers the registers, except the program counter and the four general purpose register banks, reside in the special function register area. the 94 special function registers (sfrs) in the standard and mapped sfr area include pointers and registers that provide an interface between the cpu and the other on-chip peripherals. all sfrs with addresses where address bits 0-2 are 0 (e.g. 80 h , 88 h , 90 h , 98 h , , f8 h , ff h ) are bitaddressable. the sfrs of the c517a are listed in table 3 and table 4 . in table 3 they are organized in groups which refer to the functional blocks of the c517a. table 4 illustrates the contents of the sfrs in numeric order of their addresses.
c517a semiconductor group 20 1997-10-01 table 3 special function registers - functional blocks block symbol name address contents after reset cpu acc b dph dpl dpsel psw sp accumulator b-register data pointer, high byte data pointer, low byte data pointer select register program status word register stack pointer e0 h 1) f0 h 1) 83 h 82 h 92 h d0 h 1) 81 h 00 h 00 h 00 h 00 h xxxx x000 b 3) 00 h 07 h a/d- converter adcon0 2) adcon1 addath addatl a/d converter control register 0 a/d converter control register 1 a/d converter data register, high byte a/d converter data register, low byte d8 h 1) dc h d9 h da h 00 h 0xxx 0000 b 3) 00 h 00xx xxxx b 3 interrupt system ien0 2) ien1 2) ien2 ip0 2) ip1 ircon0 2) ircon1 tcon 2) t2con 2) s0con 2) ctcon 2) interrupt enable register 0 interrupt enable register 1 interrupt enable register 2 interrupt priority register 0 interrupt priority register 1 interrupt request control register 0 interrupt request control register 1 timer 0/1 control register timer 2 control register serial channel 0 control register compare timer control register a8 h 1) b8 h 1) 9a h a9 h b9 h c0 h 1) d1 h 88 h 1) c8 h 1) 98 h 1) e1 h 00 h 00 h xx00 00x0 b 3) 00 h xx00 0000 b 3) 00 h 00 h 00 h 00 h 00 h 0x00 0000 b 3) mul/div unit arcon md0 md1 md2 md3 md4 md5 arithmetic control register multiplication/division register 0 multiplication/division register 1 multiplication/division register 2 multiplication/division register 3 multiplication/division register 4 multiplication/division register 5 ef h e9 h ea h eb h ec h ed h ee h 0xxxxxxx b 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) xx h 3) timer 0 / timer 1 tcon 2) th0 th1 tl0 tl1 tmod timer 0/1 control register timer 0, high byte timer 1, high byte timer 0, low byte timer 1, low byte timer mode register 88 h 1) 8c h 8d h 8a h 8b h 89 h 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved
semiconductor group 21 1997-10-01 c517a compare/ capture unit (ccu) timer 2 ccen cc4en cch1 cch2 cch3 cch4 ccl1 ccl2 ccl3 ccl4 cmen cmh0 cmh1 cmh2 cmh3 cmh4 cmh5 cmh6 cmh7 cml0 cml1 cml2 cml3 cml4 cml5 cml6 cml7 cmsel crch crcl comsetl comseth comclrl comclrh setmsk clrmsk ctcon 2) ctrelh ctrell th2 tl2 t2con 2) ircon0 2) compare/capture enable register compare/capture 4 enable register compare/capture register 1, high byte compare/capture register 2, high byte compare/capture register 3, high byte compare/capture register 4, high byte compare/capture register 1, low byte compare/capture register 2, low byte compare/capture register 3, low byte compare/capture register 4, low byte compare enable register compare register 0, high byte compare register 1, high byte compare register 2, high byte compare register 3, high byte compare register 4, high byte compare register 5, high byte compare register 6, high byte compare register 7, high byte compare register 0, low byte compare register 1, low byte compare register 2, low byte compare register 3, low byte compare register 4, low byte compare register 5, low byte compare register 6, low byte compare register 7, low byte compare input select comp./rel./capt. register high byte comp./rel./capt. register low byte compare set register low byte compare set register, high byte compare clear register, low byte compare clear register, high byte compare set mask register compare clear mask register compare timer control register compare timer rel. register, high byte compare timer rel. register, low byte timer 2, high byte timer 2, low byte timer 2 control register interrupt request control register 0 c1 h c9 h c3 h c5 h c7 h cf h c2 h c4 h c6 h ce h f6 h d3 h d5 h d7 h e3 h e5 h e7 h f3 h f5 h d2 h d4 h d6 h e2 h e4 h e6 h f2 h f4 h f7 h cb h ca h a1 h a2 h a3 h a4 h a5 h a6 h e1 h df h de h cd h cc h c8 h 1) c0 h 1) 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 00 h 0x00 0000 b 3 ) 00 h 00 h 00 h 00 h 00 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved table 3 special function registers - functional blocks (contd) block symbol name address contents after reset
c517a semiconductor group 22 1997-10-01 ports p0 p1 p2 p3 p4 p5 p6 p7 p8 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7, analog/digital input port 8, analog/digital input, 4-bit 80 h 1) 90 h 1) a0 h 1) b0 h 1) e8 h 1) f8 h 1) fa h db h dd h ff h ff h ff h ff h ff h ff h ff h C C xram xpage syscon 2) page address register for extended on-chip ram system/xram control register 91 h b1 h 00 h xxxx xx01 b 3) serial channels adcon0 2) pcon 2) s0buf s0con s0rell s0relh s1buf s1con s1rell s1relh a/d converter control register power control register serial channel 0 buffer register serial channel 0 control register serial channel 0 reload reg., low byte serial channel 0 reload reg., high byte serial channel 1 buffer register serial channel 1 control register serial channel 1 reload reg., low byte serial channel 1 reload reg., high byte d8 h 1) 87 h 99 h 98 h 1) aa h ba h 9c h 9b h 9d h bb h 00 h 00 h xx h 3 ) 00 h d9 h xxxx xx11 b 3) xx h 3 ) 0x00 0000 b 3) 00 h xxxx xx11 b 3) watchdog ien0 2) ien1 2) ip0 2) wdtrel interrupt enable register 0 interrupt enable register 1 interrupt priority register 0 watchdog timer reload register a8 h 1) b8 h 1) a9 h 86 h 00 h 00 h 00 h 00 h pow. sav. modes pcon 2) power control register 87 h 00 h 1) bit-addressable special function registers 2) this special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) x means that the value is undefined and the location is reserved. table 3 special function registers - functional blocks (contd) block symbol name address contents after reset
semiconductor group 23 1997-10-01 c517a table 4 contents of the sfrs, sfrs in numeric order of their addresses addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 h 2) p0 ff h .7 .6 .5 .4 .3 .2 .1 .0 81 h sp 07 h .7 .6 .5 .4 .3 .2 .1 .0 82 h dpl 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h dph 00 h .7 .6 .5 .4 .3 .2 .1 .0 83 h wdtrel 00 h wdt- psel .6 .5 .4 .3 .2 .1 .0 87 h pcon 00 h smod pds idls sd gf1 gf0 pde idle 88 h 2) tcon 00 h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 89 h tmod 00 h gate c/ t m1 m0 gate c/ tm1 m0 8a h tl0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8b h tl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 8c h th0 00 h .7 .6 .5 .4 .3 .2 .1 .0 8d h th1 00 h .7 .6 .5 .4 .3 .2 .1 .0 90 h 2) p1 ff h t2 clk- out t2ex int2 int6 int5 int4 int3 91 h xpage 00 h .7 .6 .5 .4 .3 .2 .1 .0 92 h dpsel xxxx- x000 b CCCCC.2.1.0 98 h 2) s0con 00 h sm0 sm1 sm20 ren0 tb80 rb80 ti0 ri0 99 h s0buf xx h .7 .6 .5 .4 .3 .2 .1 .0 9a h ien2 xx00- 00x0 b C C ecr ecs ect ecmp C es1 9b h s1con 0x00- 0000 b sm C sm21 ren1 tb81 rb81 ti1 ri1 9c h s1buf xx h .7 .6 .5 .4 .3 .2 .1 .0 9d h s1rell 00 h .7 .6 .5 .4 .3 .2 .1 .0 a0 h 2) p2 ff h .7 .6 .5 .4 .3 .2 .1 .0 a1 h comsetl 00 h .7 .6 .5 .4 .3 .2 .1 .0 a2 h comseth 00 h .7 .6 .5 .4 .3 .2 .1 .0 a3 h comclrl 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) shaded registers are bit-addressable special function registers
c517a semiconductor group 24 1997-10-01 a4 h comclrh 00 h .7 .6 .5 .4 .3 .2 .1 .0 a5 h setmsk 00 h .7 .6 .5 .4 .3 .2 .1 .0 a6 h clrmsk 00 h .7 .6 .5 .4 .3 .2 .1 .0 a8 h 2) ien0 00 h eal wdt et2 es0 et1 ex1 et0 ex0 a9 h ip0 00 h owds wdts .5 .4 .3 .2 .1 .0 aa h s0rell d9 h .7 .6 .5 .4 .3 .2 .1 .0 b0 h 2) p3 ff h rd wr t1 t0 int1 int0 txd0 rxd0 b1 h syscon xxxx- xx01 b CCCCCC xmap1 xmap0 b8 h 2) ien1 00 h exen2 swdt ex6 ex5 ex4 ex3 ex2 eadc b9 h ip1 xx00- 0000 b C C .5.4.3.2.1.0 ba h s0relh xxxx- xx11 b CCCCCC.1.0 bb h s1relh xxxx- xx11 b CCCCCC.1.0 c0 h 2) ircon0 00 h exf2 tf2 iex6 iex5 iex4 iex3 iex2 iadc c1 h ccen 00 h coca h3 cocal 3 coca h2 cocal 2 coca h1 cocal 1 coca h0 coca l0 c2 h ccl1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c3 h cch1 00 h .7 .6 .5 .4 .3 .2 .1 .0 c4 h ccl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c5 h cch2 00 h .7 .6 .5 .4 .3 .2 .1 .0 c6 h ccl3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c7 h cch3 00 h .7 .6 .5 .4 .3 .2 .1 .0 c8 h 2) t2con 00 h t2ps i3fr i2fr t2r1 t2r0 t2cm t2i1 t2i0 c9 h cc4en 00 h coco en1 coco n2 coco n1 coco n0 coco en0 coca h4 coca l4 como 1) x means that the value is undefined and the location is reserved 2) shaded registers are bit-addressable special function registers table 4 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
semiconductor group 25 1997-10-01 c517a ca h crcl 00 h .7 .6 .5 .4 .3 .2 .1 .0 cb h crch 00 h .7 .6 .5 .4 .3 .2 .1 .0 cc h tl2 00 h .7 .6 .5 .4 .3 .2 .1 .0 cd h th2 00 h .7 .6 .5 .4 .3 .2 .1 .0 ce h ccl4 00 h .7 .6 .5 .4 .3 .2 .1 .0 cf h cch4 00 h .7 .6 .5 .4 .3 .2 .1 .0 d0 h 2) psw 00 h cy ac f0 rs1 rs0 ov f1 p d1 h ircon1 00 h icmp7 icmp6 icmp5 icmp4 icmp3 icmp2 icmp1 icmp0 d2 h cml0 00 h .7 .6 .5 .4 .3 .2 .1 .0 d3 h cmh0 00 h .7 .6 .5 .4 .3 .2 .1 .0 d4 h cml1 00 h .7 .6 .5 .4 .3 .2 .1 .0 d5 h cmh1 00 h .7 .6 .5 .4 .3 .2 .1 .0 d6 h cml2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d7 h cmh2 00 h .7 .6 .5 .4 .3 .2 .1 .0 d8 h 2) adcon0 00 h bd clk adex bsy adm mx2 mx1 mx0 d9 h addath 00 h .9 .8 .7 .6 .5 .4 .3 .2 da h addatl 00xx- xxxx b .1.0CCCCCC db h p7 C .7.6.5.4.3.2.1.0 dc h adcon1 0xxx- 0000 b adcl C C C mx3 mx2 mx1 mx0 dd h p8 C CCCC.3.2.1.0 de h ctrell 00 h .7 .6 .5 .4 .3 .2 .1 .0 df h ctrelh 00 h .7 .6 .5 .4 .3 .2 .1 .0 e0 h 2) acc 00 h .7 .6 .5 .4 .3 .2 .1 .0 e1 h ctcon 0x00. 0000 b t2ps1 C icr ics ctf clk2 clk1 clk0 e2 h cml3 00 h .7 .6 .5 .4 .3 .2 .1 .0 1) x means that the value is undefined and the location is reserved 2) shaded registers are bit-addressable special function registers table 4 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
c517a semiconductor group 26 1997-10-01 e3 h cmh3 00 h .7 .6 .5 .4 .3 .2 .1 .0 e4 h cml4 00 h .7 .6 .5 .4 .3 .2 .1 .0 e5 h cmh4 00 h .7 .6 .5 .4 .3 .2 .1 .0 e6 h cml5 00 h .7 .6 .5 .4 .3 .2 .1 .0 e7 h cmh5 00 h .7 .6 .5 .4 .3 .2 .1 .0 e8 h 2) p4 ff h cm7 cm6 cm5 cm4 cm3 cm2 cm1 cm0 e9 h md0 xx h .7 .6 .5 .4 .3 .2 .1 .0 ea h md1 xx h .7 .6 .5 .4 .3 .2 .1 .0 eb h md2 xx h .7 .6 .5 .4 .3 .2 .1 .0 ec h md3 xx h .7 .6 .5 .4 .3 .2 .1 .0 ed h md4 xx h .7 .6 .5 .4 .3 .2 .1 .0 ee h md5 xx h .7 .6 .5 .4 .3 .2 .1 .0 ef h arcon 0xxx. xxxx b mdef mdov slr sc.4 sc.3 sc.2 sc.1 sc.0 f0 h 2) b 00 h .7 .6 .5 .4 .3 .2 .1 .0 f2 h cml6 00 h .7 .6 .5 .4 .3 .2 .1 .0 f3 h cmh6 00 h .7 .6 .5 .4 .3 .2 .1 .0 f4 h cml7 00 h .7 .6 .5 .4 .3 .2 .1 .0 f5 h cmh7 00 h .7 .6 .5 .4 .3 .2 .1 .0 f6 h cmen 00 h .7 .6 .5 .4 .3 .2 .1 .0 f7 h cmsel 00 h .7 .6 .5 .4 .3 .2 .1 .0 f8 h 2) p5 ff h ccm7 ccm6 ccm5 ccm4 ccm3 ccm2 ccm1 ccm0 fa h p6 ff h .7 .6 .5 .4 .3 txd1 rxd1 adst 1) x means that the value is undefined and the location is reserved 2) shaded registers are bit-addressable special function registers table 4 contents of the sfrs, sfrs in numeric order of their addresses (contd) addr register content after reset 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
semiconductor group 27 1997-10-01 c517a digital i/o ports the c517a allows for digital i/o on 56 lines grouped into 7 bidirectional 8-bit ports. each port bit consists of a latch, an output driver and an input buffer. read and write accesses to the i/o ports p0 through p6 are performed via their corresponding special function registers p0 to p6. the output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. in this application, port 0 outputs the low byte of the external memory address, time- multiplexed with the byte being written or read. port 2 outputs the high byte of the external memory address when the address is 16 bits wide. otherwise, the port 2 pins continue emitting the p2 sfr contents. analog input ports ports 7 (8-bit) an 8 (4-bit) are input ports only and provide two functions. when used as digital inputs, the corresponding sfr p7 and p8 contains the digital value applied to the port 7/8 lines. when used for analog inputs the desired analog channel is selected by a four-bit field in sfr adcon1. of course, it makes no sense to output a value to these input-only ports by writing to the sfr p7 or p8. this will have no effect. if a digital value is to be read, the voltage levels are to be held within the input voltage specifications ( v il / v ih ). since p7 and p8 are not bit-addressable, all input lines of p7 and p8 are read at the same time by byte instructions. nevertheless, it is possible to use port 7 and 8 simultaneously for analog and digital input. however, care must be taken that all bits of p7 and p8 that have an undetermined value caused by their analog function are masked.
c517a semiconductor group 28 1997-10-01 timer / counter 0 and 1 timer/counter 0 and 1 can be used in four operating modes as listed in table 5 : in the timer function (c/t = 0) the register is incremented every machine cycle. therefore the count rate is f osc /12. in the counter function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (p3.4/t0, p3.5/t1). since it takes two machine cycles to detect a falling edge the max. count rate is f osc /24. external inputs int0 and int1 (p3.2, p3.3) can be programmed to function as a gate to facilitate pulse width measurements. figure 9 illustrates the input clock logic. figure 9 timer/counter 0 and 1 input clock logic table 5 timer/counter 0 and 1 operating modes mode description tmod input clock m1 m0 internal external (max) 0 8-bit timer/counter with a divide-by-32 prescaler 00 f osc /12x32 f osc /24x32 1 16-bit timer/counter 1 1 f osc /12 f osc /24 2 8-bit timer/counter with 8-bit autoreload 10 3 timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer timer 1 stops 11 12 f osc /12 mcs01768 osc f c/t tmod 0 control timer 0/1 input clock tcon tr 0/1 gate tmod & =1 1 p3.4/t0 p3.5/t1 max p3.2/int0 p3.3/int1 osc /24 f 1 _ <
semiconductor group 29 1997-10-01 c517a compare / capture unit (ccu) the compare/capture unit is one of the c517as most powerful peripheral units for use in all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc. the ccu consists of two 16-bit timer/counters with automatic reload feature and an array of 13 compare or compare/capture registers. a set of six control registers is used for flexible adapting of the ccu to a wide variety of users applications. the block diagram in figure 10 shows the general configuration of the ccu. all cc1 to cc4 registers and the crc register are exclusively assigned to timer 2. each of the eight compare registers cm0 through cm7 can either be assigned to timer 2 or to the faster compare timer, e.g. to provide up to 8 pwm output channels. the assignment of the cmx registers - which can be done individually for every single register - is combined with an automatic selection of one of the two possible compare modes. figure 10 timer 2 block diagram capt./comp. mcb01577 max.clock = f osc timer 2 (cm7) 16-bit compare (cm0) 8x compare timer prescaler (ctrel) 16-bit reload comp. 4 (cc4) capt./comp. 3 (cc3) capt./comp. 2 (cc2) capt./comp. 1 (cc1) 16-bit rel.capt. (crc) "internal bus" shadow latch cc4en logik control port latch p1- i/o- i/o- p5- latch /12 max.clock = /2 osc f prescaler latch i/o- p4- logik port control
c517a semiconductor group 30 1997-10-01 the main functional blocks of the ccu are: C timer 2 with f osc /12 input clock, 2-bit prescaler, 16-bit reload, counter/gated timer mode and overflow interrupt request. C compare timer with f osc /2 input clock, 3-bit prescaler, 16-bit reload and overflow interrupt request. C compare/(reload/) capture register array consisting of four different kinds of registers: one 16-bit compare/reload/capture register, three 16-bit compare/capture registers, one 16-bit compare/capture register with additional concurrent compare feature, eight 16-bit compare registers with timer-overflow controlled loading. table 6 shows the possible configurations of the ccu and the corresponding compare modes which can be selected. the following sections describe the function of these configurations. table 6 ccu con?gurations assigned timer compare register compare output at possible modes timer 2 crch/crcl cch1/ccl1 cch2/ccl2 cch3/ccl3 cch4/ccl4 p1.0/int3/cc0 p1.1/int4/cc1 p1.2/int5/cc2 p1.3/int6/cc3 p1.4/int2/cc4 compare mode 0, 1 + reload compare mode 0, 1 / capture compare mode 0, 1 / capture compare mode 0, 1 / capture compare mode 0, 1 / capture cch4/ccl4 p1.4/int2/cc4 p5.0/ccm0 to p5.7/ccm7 compare mode 1 concurrent compare cmh0/cml0 to cmh7/cml7 p4.0/cm0 to p4.7/cm7 compare mode 0 comset comclr p5.0/ccm0 to p5.7/ccm7 compare mode 2 compare timer cmh0/cml0 to cmh7/cml7 p4.0/cm0 to p4.7/cm7 compare mode 1
semiconductor group 31 1997-10-01 c517a timer 2 operation timer mode: in timer function, the count rate is derived from the oscillator frequency. a prescaler offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency. gated timer mode: in gated timer function, the external input pin p1.7/t2 operates as a gate to the input of timer 2. if t2 is high, the internal clock input is gated to the timer. t2 = 0 stops the counting procedure. the external gate signal is sampled once every machine cycle. event counter mode: in the event counter function. the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin p1.7/t2. in this function, the external input is sampled every machine cycle. the maximum count rate is 1/24 of the oscillator frequency. reload of timer 2: two reload modes are selectable: in mode 0, when timer 2 rolls over from all 1s to all 0s, it not only sets tf2 but also causes the timer 2 registers to be loaded with the 16-bit value in the crc register, which is preset by software. in mode 1, a 16-bit reload from the crc register is caused by a negative transition at the corresponding input pin p1.5/t2ex. figure 11 block diagram of timer 2 mcb03328 programmable osc t2ps t2ps1 no input selected timer stop 00 01 10 11 counter function via ext. input p1.7/t2 timer function gated timer function by ext. input p1.7/t2 t2i1 t2i0 sfr t2con p1.7/t2 tl2 th2 tf2 exf2 interrupt exen2 sync p1.5/t2ex reload timer 2 input clock 1 1 (8 bits) (8 bits) _ < _ < prescaler
c517a semiconductor group 32 1997-10-01 compare timer operation the compare timer receives its input clock from a programmable prescaler which provides input frequencies, ranging from f osc /2 up to f osc /256. the compare timer is, once started, a free-running 16-bit timer, which on overflow is automatically reloaded by the contents of a 16-bit reload register. the compare timer has - as any other timer in the c517a - their own interrupt request flags ctf. these flags are set when the timer count rolls over from all ones to the reload value. figure 12 shows the block diagram of compare timer and compare timer 1. figure 12 compare timer block diagram 16-bit reload (ctrel) 16-bit compare timer control (ctcon) ctf overflow to interrupt circuitry to compare circuitry 16 3-bit prescaler /2 /4 /8 /16 /32 /64 /128 compare timer f osc /2 mcb00783
semiconductor group 33 1997-10-01 c517a compare modes the compare function of a timer/register combination operates as follows: the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. compare mode 0 in compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. it goes back to a low level on timer overflow. as long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. figure 13 shows a functional diagram of a port circuit when used in compare mode 0. the port latch is directly controlled by the timer overflow and compare match signals. the input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. figure 13 port latch in compare mode 0 compare mode 1 if compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. in compare mode 1 (see figure 14 ) the port circuit consists of two separate latches. one latch (which acts as a shadow latch) can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. mcs02661 latch port q q clk d port pin read pin cc v read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match s r overflow timer 16 bit bit 16
c517a semiconductor group 34 1997-10-01 figure 14 compare function in compare mode 1 compare mode 2 in the compare mode 2 the port 5 pins are under control of compare/capture register cc4, but under control of the compare registers comset and comclr. when a compare match occurs with register comset, a high level appears at the pins of port 5 when the corresponding bits in the mask register setmsk are set. when a compare match occurs with register comclr, a low level appears at the pins of port 5 when the corresponding bits in the mask register clrmsk are set. figure 15 compare function of compare mode 2 mcs02662 latch port q q clk d read pin cc v d clk q shadow latch read latch port circuit internal bus latch write to compare reg. compare register circuit comparator timer register timer circuit compare match pin port 16 bit 16 bit mcs02663 latch port q q clk d read pin cc v read latch port circuit internal bus latch write to comparator compare signal s r setmsk bits comset th2 comparator comclr timer 2 tl2 bits clrmsk signal compare pin port 16 bit 16 bit bit 16 bit 16
semiconductor group 35 1997-10-01 c517a multiplication / division unit (mdu) this on-chip arithmetic unit of the c517a provides fast 32-bit division, 16-bit multiplication as well as shift and normalize features. all operations are unsigned integer operations. table 7 describes the five general operations the mdu is able to perform. 1) 1 t cy = 12 t clcl = 1 machine cycle = 500 ns at 24 mhz oscillator frequency 2) the maximal shift speed is 6 shifts per machine cycle the mdu consists of seven special function registers (md0-md5, arcon) which are used as operand, result, and control registers. the three operation phases are shown in figure 16 . figure 16 operating phases of the mdu table 7 mdu operation characteristics operation result remainder execution time 32bit/16bit 16bit/16bit 16bit x 16bit 32-bit normalize 32-bit shift l/r 32bit 16bit 32bit C C 16bit 16bit C C C 6 t cy 1) 4 t cy 1) 4 t cy 1) 6 t cy 2) 6 t cy 2)
c517a semiconductor group 36 1997-10-01 for starting an operation, registers md0 to md5 and arcon must be written to in a certain sequence according table 8 and 9 . the order the registers are accessed determines the type of the operation. a shift operation is started by a final write operation to sfr arcon. abbreviations: d'end : dividend, 1st operand of division d'or : divisor, 2nd operand of division m'and : multiplicand, 1st operand of multiplication m'or : multiplicator, 2nd operand of multiplication pr : product, result of multiplication rem : remainder quo : quotient, result of division ...l : means, that this byte is the least significant of the 16-bit or 32-bit operand ...h : means, that this byte is the most significant of the 16-bit or 32-bit operand table 8 programming the mdu for multiplication and division operation 32bit/16bit 16bit/16bit 16bit x 16bit first write last write md0 dendl md1 dend md2 dend md3 dendh md4 dorl md5 dorh md0 dendl md1 dendh md4 dorl md5 dorh md0 mandl md4 morl md1 mandh md5 morh first read last read md0 quol md1 quo md2 quo md3 quoh md4 reml md5 remh md0 quol md1 quoh md4 reml md5 remh md0 prl md1 md2 md3 prh table 9 programming of the mdu for a shift or normalize operation operation normalize, shift left, shift right first write last write md0 least significant byte md1 . md2 . md3 most significant byte arcon start of conversion first read last read md0 least significant byte md1 . md2 . md3 most significant byte
semiconductor group 37 1997-10-01 c517a serial interfaces 0 and 1 the c517a has two serial interfaces which are functionally nearly identical concerning the asynchronous modes of operation. the two channels are full-duplex, meaning they can transmit and receive simultaneously. the serial channel 0 is completely compatible with the serial channel of the c501 (one synchronous mode, three asynchronous modes). serial channel 1 has the same functionality in its asynchronous modes, but the synchronous mode and the fixed baud rate uart mode is missing. the operating modes of the serial interfaces is illustrated in table 10 . the possible baudrates can be calculated using the formulas given in table 11 . table 10 operating modes of serial interface 0 and 1 serial interface mode s0con s1con description sm0 sm1 sm 0 0 0 0 C shift register mode serial data enters and exits through r d0; t d0 outputs the shift clock; 8-bit are transmitted/received (lsb first); fixed baud rate 1 0 1 C 8-bit uart, variable baud rate 10 bits are transmitted (through t d0) or received (at r d0) 2 1 0 C 9-bit uart, fixed baud rate 11 bits are transmitted (through t d0) or received (at r d0) 3 1 1 C 9-bit uart, variable baud rate like mode 2 1 a C C 0 9-bit uart; variable baud rate 11 bits are transmitted (through t d1) or received (at r d1) b C C 1 8-bit uart; variable baud rate 10 bits are transmitted (through t d1) or received (at r d1)
c517a semiconductor group 38 1997-10-01 for clarification some terms regarding the difference between baud rate clock and baud rate should be mentioned. in the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. therefore, the baud rate generators/timers have to provide a baud rate clock (output signal in figure 17 and figure 18 ) to the serial interface which - there divided by 16 - results in the actual baud rate. further, the abbreviation f osc refers to the oscillator frequency (crystal or external clock operation). the variable baud rates for modes 1 and 3 of the serial interface 0 can be derived from either timer 1 or a dedicated baud rate generator (see figure 17 ). the variable baud rates for modes a and b of the serial interface 1 are derived from a dedicated baud rate generator as shown in figure 18 . figure 17 serial interface 0 : baud rate generation configuration figure 18 serial interface 1 : baud rate generator configuration the baud rate generator block in figure 17 has the same structure (10-bit auto-reload timer) as the baud rate generator block which is shown in detail in figure 18 . mcs03329 f osc (sm0/ sm1) s0con.7 s0con.6 only one mode can be selected adcon0.7 (bd) 0 1 timer 1 overflow note : the switch configuration shows the reset state. mode 3 mode 1 6 /2 mode 2 mode 0 baud rate generator (s0relh s0rell) 2 (smod) pcon.7 1 0 rate baud clock mcs03331 baud rate generator s1relh .1 .0 s1rell 10-bit timer input clock baud owerflow f /2 osc rate clock
semiconductor group 39 1997-10-01 c517a table 11 below lists the values/formulas for the baud rate calculation of serial interface 0 and 1 with its dependencies of the control bits bd and smod. table 11 serial interfaces - baud rate dependencies serial interface operating modes active control bits baud rates smod bd mode 0 (shift register) C C fixed baud rate clock fosc/12 mode 1 (8-bit uart) mode 3 (9-bit uart) x 0 timer 1 overflow is used for baud rate generation; smod controls a divide-by-2 option. baud rate = 2 smod x timer 1 overflow rate / 32 1 baud rate generator is used for baud rate generation; smod controls a divide-by-2 option baud rate = 2 smod x oscillator frequency / 64 x (baud rate gen. overflow rate) mode 2 (9-bit uart) x C fixed baud rate clock fosc/32 (smod=1) or fosc/ 64 (smod=0) mode a (9-bit uart) mode b (8-bit uart) C C baud rate generator is used for baud rate generation; smod controls a divide-by-2 option baud rate = oscillator frequency / 32 x (baud rate gen. overflow rate)
c517a semiconductor group 40 1997-10-01 10-bit a/d converter the c517a provides an a/d converter with the following features: C 12 multiplexed input channels (port 7, 8), which can also be used as digital inputs C 10-bit resolution C single or continuous conversion mode C internal or external start-of-conversion trigger capability C interrupt request generation after each conversion C using successive approximation conversion technique via a capacitor array C built-in hidden calibration of offset and linearity errors the a/d converter operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. the externally applied reference voltage range has to be held on a fixed value within the specifications. the main functional blocks of the a/d converter are shown in figure 19 .
semiconductor group 41 1997-10-01 c517a figure 19 a/d converter block diagram a/d converter addath addatl adcon0 (d8 ) internal mux port 7 s&h f adc osc f v aref v agnd p6.0/adst shaded bit locations are not used in adc-functions mcb03332 single/ continuous mode ) (d9 (da ) h clock prescaler 8, 4 p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 adcon1 (dc ) h p7 (db ) h p8 (dd ) h ircon0 (c0 ) h ien1 (b8 ) h port 8 bus /2 write to addatl conversion clock input clock in f start of conversion internal bus iex5 bsy ex5 clk adcl bd adex __ tf2 _ exf2 __ iex6 swdt exen2 ex6 mx3 adm _ mx2 mx1 mx2 mx1 iex3 p8.3 _ iex4 p8.2 p8.1 iex2 mx0 mx0 p8.0 iadc eadc ex4 ex3 ex2 .8 msb .6 .7 .4 .5 .2 .3 .1 lsb _ _ _ _ _ _ hh
c517a semiconductor group 42 1997-10-01 interrupt system the c517a provides 17 interrupt sources with four priority levels. ten interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, compare timer, compare match/set/clear, a/d converter, and serial interface 0 and 1) and seven interrupts may be triggered externally (p3.2/int0, p3.3/int1, p1.4/int2, p1.0/ int3, p1.1/int4, p1.2/int5, p1.3/int6). this chapter shows the interrupt structure, the interrupt vectors and the interrupt related special function registers. figure 20 to 22 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections.
semiconductor group 43 1997-10-01 c517a figure 20 interrupt structure, overview (part 1) mcs03333 bit addressable request flag is cleared by hardware ip1.0 h 0003 tcon.1 ien0.0 ie0 ex0 p3.2/ it0 tcon.0 ip0.0 highest priority level es1 ri1 ien2.0 s1con.0 0083 h uart 1 timer 0 h 000b tcon.5 ien0.1 tf0 et0 overflow int0 int2/ t2con.5 i2fr p1.4/ ex2 iex2 ien1.1 ircon0.1 lowest priority level eal ien0.7 polling sequence 004b h ip0.1 ip1.1 1 _ < ti1 s1con.1 cc4 a/d converter 0043 ircon0.0 ien1.0 eadc iadc h
c517a semiconductor group 44 1997-10-01 figure 21 interrupt structure, overview (part 2) mcs03334 bit addressable request flag is cleared by hardware ip1.2 h 0013 tcon.3 ien0.2 ie1 ex1 p3.3/ it1 tcon.2 ip0.2 highest priority level ecmp ien2.2 0093 h match in cm0-cm7 timer 1 h 001b tcon.7 ien0.3 tf1 et1 overflow int1 ect ctf ien2.3 ctcon.3 lowest priority level eal ien0.7 polling sequence 009b h ip0.3 ip1.3 0053 h ircon1.0-7 icmp0-7 i3fr t2con.5 cc0 p1.0/ int3/ ircon0.2 ien1.2 iex3 ex3 overflow compare timer ircon0.3 iex4 005b ien1.3 ex4 h cc1 int4/ p1.1/
semiconductor group 45 1997-10-01 c517a figure 22 interrupt structure, overview (part 3) mcs03335 bit addressable request flag is cleared by hardware ip1.4 h 0023 ip0.4 highest priority level es0 ri0 ien0.4 s0con.0 00a3 h usart 0 timer 2 h 002b ien0.5 et2 overflow int6/ p1.3/ ex6 iex6 ien1.5 ircon0.5 lowest priority level eal ien0.7 polling sequence 006b h ip0.5 ip1.5 1 _ < ti0 s0con.1 cc3 0063 ircon0.4 ien1.4 ex5 iex5 h ctcon.4 ecs ien2.4 ics tf2 ircon0.6 _ < 1 00ab ctcon.5 ien2.5 icr ecr h ircon0.7 exf2 ien1.7 exen2 p1.2/ int5/ cc2 p1.5/ t2ex match in comset match in comclr
c517a semiconductor group 46 1997-10-01 table 12 interrupt source and vectors interrupt source interrupt vector address interrupt request flags external interrupt 0 0003 h ie0 timer 0 overflow 000b h tf0 external interrupt 1 0013 h ie1 timer 1 overflow 001b h tf1 serial channel 0 0023 h ri0 / ti0 timer 2 overflow / ext. reload 002b h tf2 / exf2 a/d converter 0043 h iadc external interrupt 2 004b h iex2 external interrupt 3 0053 h iex3 external interrupt 4 005b h iex4 external interrupt 5 0063 h iex5 external interrupt 6 006b h iex6 serial channel 1 0083 h ri1 / ti1 compare match interrupt of compare registers cm0-cm7 assigned to timer 2 0093 h icmp0 - icmp7 compare timer overflow 009b h ctf compare match interrupt of compare register comset 00a3 h ics compare match interrupt of compare register comclr 00ab h icr
semiconductor group 47 1997-10-01 c517a fail save mechanisms the c517a offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure: C a programmable watchdog timer (wdt), with variable time-out period from 512 m s up to approx. 1.1 s at 12 mhz. (256 m s up to approx. 0.65 s at 24 mhz) C an oscillator watchdog (owd) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. the watchdog timer in the c517a is a 15-bit timer, which is incremented by a count rate of f osc /24 up to f osc /384. the system clock of the c517a is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. for programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog timer can be written. figure 23 shows the block diagram of the watchdog timer unit. figure 23 block diagram of the watchdog timer the watchdog timer can be started by software (bit swdt) or by hardware through pin pe/swd, but it cannot be stopped during active mode of the c517a. if the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. for refreshing of the watchdog timer the content of the sfr wdtrel is transferred to the upper 7-bit of the watchdog timer. the refresh sequence consists of two consecutive instructions which set the bits wdt and swdt each. the reset cause (external reset or reset caused by the watchdog) can be examined by software (flag wdts). it must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. mcb03250 ip0 (a9 ) h osc f wdts - ------ 2 16 14 07 8 wdtl wdth /12 external hw reset external hw power-down pe/swd control logic ien0 (a8 ) h ien1 (b8 ) h 6 70 wdt reset-request wdtpsel wdtrel (86 ) h - wdt -- - - -- - swdt -- - - --
c517a semiconductor group 48 1997-10-01 oscillator watchdog the oscillator watchdog unit serves for four functions: C monitoring of the on-chip oscillator's function the watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary rc oscillator in the watchdog unit, the internal clock is supplied by the rc oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on- chip oscillator has a higher frequency than the rc oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again. C fast internal reset after power-on the oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. the oscillator watchdog unit also works identically to the monitoring function. C restart from the hardware power down mode. if the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. the oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function. figure 24 block diagram of the oscillator watchdog owds 1 ip0 (a9 ) frequency comparator delay f 2 < 1 f f 1 2 f internal clock on-chip oscillator oscillator rc xtal1 xtal2 rc f 3mhz mcb03337 h 5 2 _ < internal reset
semiconductor group 49 1997-10-01 c517a power saving modes the c517a provides two basic power saving modes, the idle mode and the power down mode. additionally, a slow down mode is available. this power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. C idle mode the cpu is gated off from the oscillator. all peripherals are still provided with the clock and are able to work. idle mode is entered by software and can be left by an interrupt or reset. C slow down mode the controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 8. this slows down all parts of the controller, the cpu and all peripherals, to 1/8th of their normal operating frequency and also reduces power consumption. C software power down mode the operation of the c517a is completely stopped and the oscillator is turned off. this mode is used to save the contents of the internal ram with a very low standby current. this power down mode is entered by software and can be left by reset or by a short low pulse at pin p3.2/ int0. C hardware power down mode if pin hwpd gets active (low level) the part enters the hardware power down mode and starts a complete internal reset sequence. thereafter, both oscillators of the chip are stopped and the port pins and several control lines enter a floating state. in the power down mode of operation, v cc can be reduced to minimize power consumption. it must be ensured, however, that v cc is not reduced before the power down mode is invoked, and that v cc is restored to its normal operating level, before the power down mode is terminated. table 13 gives a general overview of the entry and exit procedures of the power saving modes.
c517a semiconductor group 50 1997-10-01 table 13 power saving modes overview mode entering 2-instruction example leaving by remarks idle mode orl pcon, #01h orl pcon, #20h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with clock hardware reset slow down mode in normal mode: orl pcon,#10h anl pcon,#0efh or hardware reset internal clock rate is reduced to 1/8 of its nominal frequency with idle mode: orl pcon,#01h orl pcon, #30h occurrence of an interrupt from a peripheral unit cpu clock is stopped; cpu maintains their data; peripheral units are active (if enabled) and provided with 1/8 of its nominal frequency hardware reset software power down mode orl pcon, #02h orl pcon, #40h hardware reset oscillator is stopped; contents of on-chip ram and sfrs are maintained; short low pulse at pin p3.2/ int0 hardware power down mode hwpd = 0 hwpd = 1 oscillator is stopped; internal reset is executed;
semiconductor group 51 1997-10-01 c517a absolute maximum ratings ambient temperature under bias ( t a ) ......................................................... C 40 to 125 c storage temperature ( t stg ) .......................................................................... C 65 c to 150 c voltage on v cc pins with respect to ground ( v ss ) ....................................... C 0.5 v to 6.5 v voltage on any pin with respect to ground ( v ss ) ......................................... C 0.5 v to v cc +0.5 v input current on any pin during overload condition ..................................... C 10 ma to 10 ma absolute sum of all input currents during overload condition ..................... i 100 ma i power dissipation........................................................................................ tbd note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for longer periods may affect device reliability. during overload conditions ( v in > v cc or v in < v ss ) the voltage on v cc pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings.
c517a semiconductor group 52 1997-10-01 dc characteristics v cc = 5 v + 10%, C 15%; v ss =0v t a = 0 to 70 c for the sab-c517a t a = C 40 to 85 c for the saf-c517a t a = C 40 to 110 c for the sah-c517a notes see next page parameter symbol limit values unit test condition min. max. input low voltage pins except ea, reset, hwpd ea pin hwpd and reset pins v il v il1 v il2 C 0.5 C 0.5 C 0.5 0.2 v cc C 0.1 0.2 v cc C 0.3 0.2 v cc + 0.1 v v v C C C input high voltage pins except reset, xtal2 and hwpd xtal2 pin reset and hwpd pin v ih v ih1 v ih2 0.2 v cc + 0.9 0.7 v cc 0.6 v cc v cc + 0.5 v cc + 0.5 v cc + 0.5 v v v C C C output low voltage ports 1, 2, 3, 4, 5, 6 port 0, ale, psen, ro v ol v ol1 C C 0.45 0.45 v v i ol = 1.6 ma 1) i ol = 3.2 ma 1) output high voltage ports 1, 2, 3, 4, 5, 6 port 0 in external bus mode, ale, psen, ro v oh v oh1 2.4 0.9 v cc 2.4 0.9 v cc C C C C v v v v i oh = C 80 m a i oh = C 10 m a i oh = C 800 m a i oh = C 80 m a 2) logic 0 input current ports 1, 2, 3, 4, 5, 6 i li C 10 C 70 m a v i n = 0.45 v logical 0-to-1 transition current, ports 1, 2, 3, 4, 5, 6 i tl C 65 C 650 m a v i n =2 v input leakage current port 0, 7 and 8, ea, hwpd i li C 1 m a 0.45 < v i n < v cc input low current to reset for reset xtal2 pe/swd, owe i il2 i il3 i il4 C 10 C C C 100 C 15 C 20 m a m a m a v in = 0.45 v v i n = 0.45 v v i n = 0.45 v pin capacitance c io C10pf f c = 1 mhz, t a =25 c overload current i ov C 5ma 7) 8)
semiconductor group 53 1997-10-01 c517a power supply current notes: 1) capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and port 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. in the worst case (capacitive loading > 100 pf), the noise pulse on ale line may exceed 0.8 v. in such cases it may be desirable to qualify ale with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9 v cc specification when the address lines are stabilizing. 3) i pd (power-down mode) is measured under following conditions: ea = reset = port 0 = port 7 = port 8 = v cc ; xtal1 = n.c.; xtal2 = v ss ; pe/swd = owe = v ss ; hwpd = v cc for software power-down mode; v agnd = v ss ; v aref = v cc ; all other pins are disconnected. i pd (hardware power-down mode) is independent of any particular pin connection. 4) i cc (active mode) is measured with: xtal2 driven with t clch , t chcl = 5 ns , v il = v ss + 0.5 v, v ih = v cc C 0.5 v; xtal1 = n.c.; ea = pe/swd == v ss ; port 0 = port 7 = port 8 = v cc ; hwpd = v cc ; reset = v cc ; all other pins are disconnected. 5) i cc (idle mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5 v, v ih = v cc C 0.5 v; xtal1 = n.c.; reset = v cc ; hwpd = port 0 = port 7 = port 8 = v cc ;ea= pe/swd = v ss ; all other pins are disconnected; 6) i cc (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; xtal2 driven with t clch , t chcl = 5 ns , v il = v ss + 0.5 v, v ih = v cc C 0.5 v; xtal1 = n.c.; hwpd = v cc ; reset = v cc ; port 7 = port 8 = v cc ;; ea = pe/swd == v ss ; all other pins are disconnected. 7) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v cc + 0.5 v or v ov < v ss - 0.5 v). the supply voltage v cc and v ss must remain within the specified limits. the absolute sum of input currents on all port pins may not exceed 50 ma. 8) not 100% tested, guaranteed by design characterization 9) the typical i cc values are periodically measured at t a = +25 c and v cc = 5 v but not 100% tested. 10)the maximum i cc values are measured under worst case conditions ( t a = 0 c or -40 c and v cc = 5.5 v) parameter symbol limit values unit test condition typ. 9) max. 10) active mode 18 mhz 24 mhz i cc i cc 21.3 27.3 29.2 37.6 ma ma 4) idle mode 18 mhz 24 mhz i cc i cc 11.6 14.6 16.2 20.4 ma ma 5) active mode with slow-down enabled 18 mhz 24 mhz i cc i cc 9.5 10.7 13.1 14.9 ma ma 6) power-down mode i pd 15 50 m a v cc =2 ? 5.5 v 3)
c517a semiconductor group 54 1997-10-01 figure 25 icc diagram note : f osc is the oscillator frequency in mhz. i cc values are given in ma. table 14 power supply current calculation formulas parameter symbol formula active mode i cc typ i cc max 1 * f osc + 3.3 1.4 * f osc + 4.0 idle mode i cc typ i cc max 0.5 * f osc + 2.6 0.7 * f osc + 3.6 active mode with slow-down enabled i cc typ i cc max 0.25 * f osc + 4.95 0.3 * f osc + 7.7 mcd03338 0 0 f osc cc i 3.5 8 12 16 20 24 mhz ma cc typ i i cc max 10 20 30 40 active mode idle mode idle mode active mode active + slow down mode
semiconductor group 55 1997-10-01 c517a a/d converter characteristics v cc = 5 v + 10%, C 15%; v ss =0v t a = 0 to 70 c for the sab-c517a t a = C 40 to 85 c for the saf-c517a t a = C 40 to 110 c for the sah-c517a 4 v v aref v cc +0.1 v; v ss -0.1 v v agnd v ss +0.2 v notes see next page. clock calculation table: further timing conditions: t adc min = 500 ns t in = 2 / f osc = 2 t clcl parameter symbol limit values unit test condition min. max. analog input voltage v ain v agnd v aref v 1) sample time t s C 16 x t in 8 x t in ns prescaler ? 8 prescaler ? 4 2) conversion cycle time t adcc C 96 x t in 48 x t in ns prescaler ? 8 prescaler ? 4 3) total unadjusted error t ue C 2 lsb v ss +0.5v v in v cc -0.5v 4) internal resistance of reference voltage source r aref C t adc / 250 - 0.25 k w t adc in [ns] 5) 6) internal resistance of analog source r asrc C t s / 500 - 0.25 k w t s in [ns] 2) 6) adc input capacitance c ain C50pf 6) clock prescaler ratio adcl t adc t s t adcc ? 8 1 8 x t in 16 x t in 96 x t in ? 4 0 4 x t in 8 x t in 48 x t in
c517a semiconductor group 56 1997-10-01 notes: 1) v ain may exceed v agnd or v aref up to the absolute maximum ratings. however, the conversion result in these cases will be x000 h or x3ff h , respectively. 2) during the sample time the input capacitance c ain can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach their final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. 3) this parameter includes the sample time t s , the time for determining the digital result and the time for the calibration. values for the conversion clock t adc depend on programming and can be taken from the table on the previous page. 4) t ue is tested at v aref = 5.0 v, v agnd = 0 v, v cc = 4.9 v. it is guaranteed by design characterization for all other voltages within the defined voltage range. if an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 ma, an additional conversion error of 1/2 lsb is permissible. 5) during the conversion the adcs capacitance must be repeatedly charged or discharged. the internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. the maximum internal resistance results from the programmed conversion timing. 6) not 100% tested, but guaranteed by design characterization.
semiconductor group 57 1997-10-01 c517a ac characteristics (18 mhz) v cc = 5 v + 10%, C 15%; v ss =0v t a = 0 to 70 c for the sab-c517a t a = C 40 to 85 c for the saf-c517a t a = C 40 to 110 c for the sah-c517a ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c517a to devices with float times up to 45 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. ale pulse width t lhll 71 C 2 t clcl C 40 C ns address setup to ale t avll 26 C t clcl C 30 C ns address hold after ale t llax 26 C t clcl C 30 C ns ale low to valid instruction in t lliv C 122 C 4 t clcl C 100 ns ale to psen t llpl 31 C t clcl C 25 C ns psen pulse width t plph 132 C 3 t clcl C 35 C ns psen to valid instruction in t pliv C92C 3 t clcl C 75 ns input instruction hold after psen t pxix 0C0Cns input instruction float after psen t pxiz *) C46C t clcl C 10 ns address valid after psen t pxav *) 48 C t clcl C 8 C ns address to valid instr in t aviv C 180 C 5 t clcl C 98 ns address float to psen t azpl 0C0Cns
c517a semiconductor group 58 1997-10-01 ac characteristics (18 mhz, contd) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 18 mhz clock variable clock 1/ t clcl = 3.5 mhz to 18 mhz min. max. min. max. rd pulse width t rlrh 233 C 6 t clcl C 100 C ns wr pulse width t wlwh 233 C 6 t clcl C 100 C ns address hold after ale t llax2 81 C 2 t clcl C 30 C ns rd to valid data in t rldv C 128 C 5 t clcl C 150 ns data hold after rd t rhdx 0C0Cns data float after rd t rhdz C51C 2 t clcl C 60 ns ale to valid data in t lldv C 294 C 8 t clcl C 150 ns address to valid data in t avdv C 335 C 9 t clcl C 165 ns ale to wr or rd t llwl 117 217 3 t clcl C 50 3 t clcl + 50 ns address valid to wr or rd t avwl 92 C 4 t clcl C 130 C ns wr or rd high to ale high t whlh 16 96 t clcl C 40 t clcl + 40 ns data valid to wr transition t qvwx 11 C t clcl C 45 C ns data setup before wr t qvwh 239 C 7 t clcl C 150 C ns data hold after wr t whqx 16 C t clcl C 40 C ns address float after rd t rlaz C0C0ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 18 mhz min. max. oscillator period t clcl 55.6 285.7 ns high time t chcx 15 t clcl C t clcx ns low time t clcx 15 t clcl C t chcx ns rise time t clch C15ns fall time t chcl C15ns
semiconductor group 59 1997-10-01 c517a ac characteristics (24 mhz) v cc = 5 v + 10%, C 15%; v ss =0v t a = 0 to 70 c for the sab-c517a t a = C 40 to 85 c for the saf-c517a t a = C 40 to 110 c for the sah-c517a ( c l for port 0, ale and psen outputs = 100 pf; c l for all other outputs = 80 pf) program memory characteristics *) interfacing the c517a to devices with float times up to 37 ns is permissible. this limited bus contention will not cause any damage to port 0 drivers. parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. ale pulse width t lhll 43 C 2 t clcl C 40 C ns address setup to ale t avll 17 C t clcl C 25 C ns address hold after ale t llax 17 C t clcl C 25 C ns ale low to valid instruction in t lliv C80C 4 t clcl C 87 ns ale to psen t llpl 22 C t clcl C 20 C ns psen pulse width t plph 95 C 3 t clcl C 30 C ns psen to valid instruction in t pliv C60C 3 t clcl C 65 ns input instruction hold after psen t pxix 0C0Cns input instruction float after psen t pxiz *) C32C t clcl C 10 ns address valid after psen t pxav *) 37 C t clcl C 5 C ns address to valid instr in t aviv C 148 C 5 t clcl C 60 ns address float to psen t azpl 0C0Cns
c517a semiconductor group 60 1997-10-01 ac characteristics (24 mhz, contd) external data memory characteristics external clock drive characteristics parameter symbol limit values unit 24 mhz clock variable clock 1/ t clcl = 3.5 mhz to 24 mhz min. max. min. max. rd pulse width t rlrh 180 C 6 t clcl C 70 C ns wr pulse width t wlwh 180 C 6 t clcl C 70 C ns address hold after ale t llax2 53 C 2 t clcl C 30 C ns rd to valid data in t rldv C 118 C 5 t clcl C 90 ns data hold after rd t rhdx 0C0Cns data float after rd t rhdz C63C 2 t clcl C 20 ns ale to valid data in t lldv C 200 C 8 t clcl C 133 ns address to valid data in t avdv C 220 C 9 t clcl C 155 ns ale to wr or rd t llwl 75 175 3 t clcl C 50 3 t clcl + 50 ns address valid to wr or rd t avwl 67 C 4 t clcl C 97 C ns wr or rd high to ale high t whlh 17 67 t clcl C 25 t clcl + 25 ns data valid to wr transition t qvwx 5C t clcl C 37 C ns data setup before wr t qvwh 170 C 7 t clcl C 122 C ns data hold after wr t whqx 15 C t clcl C 27 C ns address float after rd t rlaz C0C0ns parameter symbol limit values unit variable clock freq. = 3.5 mhz to 24 mhz min. max. oscillator period t clcl 41.7 285.7 ns high time t chcx 12 t clcl C t clcx ns low time t clcx 12 t clcl C t chcx ns rise time t clch C12ns fall time t chcl C12ns
semiconductor group 61 1997-10-01 c517a figure 26 program memory read cycle mct00096 ale psen port 2 lhll t a8 - a15 a8 - a15 a0 - a7 instr.in a0 - a7 port 0 t avll plph t t llpl t lliv t pliv t azpl t llax t pxiz t pxix t aviv t pxav
c517a semiconductor group 62 1997-10-01 figure 27 data memory read cycle mct00097 ale psen port 2 whlh t port 0 rd t lldv t rlrh t llwl t rldv t avll t llax2 t rlaz t avwl t avdv t rhdx t rhdz a0 - a7 from ri or dpl from pcl a0 - a7 instr. in data in a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph
semiconductor group 63 1997-10-01 c517a figure 28 data memory write cycle figure 29 external clock drive on xtal2 mct00098 ale psen port 2 whlh t port 0 wr t wlwh t llwl t qvwx t avll t llax2 t qvwh t avwl t whqx a0 - a7 from ri or dpl from pcl a0 - a7 instr.in data out a8 - a15 from pch p2.0 - p2.7 or a8 - a15 from dph mct00033 t chcx t clcx chcl t clch t v cc t clcl - 0.5v 0.45v cc 0.7 v v - 0.1 cc 0.2
c517a semiconductor group 64 1997-10-01 rom verification characteristics for the c517a-1rm rom verification mode 1 figure 30 rom verification mode 1 parameter symbol limit values unit min. max. address to valid data t avqv C10 t clcl ns p1.0-p1.7 p2.0-p2.6 port 0 mcs03253 address new address new data out data out t avqv data: addresses: p0.0-p0.7 p1.0-p1.7 p2.0-p2.6 = = = d0-d7 a0-a7 a8-a14 v reset = il2 psen inputs: = = ale, ea ss v v ih
semiconductor group 65 1997-10-01 c517a rom verification mode 2 figure 31 rom verification mode 2 parameter symbol limit values unit min. typ max. ale pulse width t awd C2 t clcl Cns ale period t acy C12 t clcl Cns data valid after ale t dva CC4 t clcl ns data stable after ale t dsa 8 t clcl CCns p3.5 setup to ale low t as C t clcl Cns oscillator frequency 1/ t clcl 3.5 C 24 mhz mct02613 t acy t awd t dsa dva t t as data valid ale port 0 p3.5
c517a semiconductor group 66 1997-10-01 figure 32 ac testing: input, output waveforms figure 33 ac testing: float waveforms figure 34 recommended oscillator circuits for crystal oscillator ac inputs during testing are driven at v cc - 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ihmin for a logic 1 and v ilmax for a logic 0. 0.45 v v cc 0.2 -0.1 +0.9 0.2 cc v test points mct00039 v cc -0.5 v for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh / v ol level occurs. i ol / i oh 3 20 ma mct00038 v load v load -0.1 v +0.1 v load v timing reference points v oh -0.1 v +0.1 v ol v 3.5-24 mhz xtal1 xtal2 = 20 pf (incl. stray capacitance) 10 pf crystal oscillator mode xtal2 xtal1 driving from external source n.c. external oscillator signal mcs03339 c c c crystal mode :
semiconductor group 67 1997-10-01 c517a figure 35 p-mqfp-100-2 package outlines gpm05623 plastic package, p-mqfp-100-2 (smd) (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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